Pcmcia memory write access – AMD Am79C930 User Manual
Page 132
AMD
P R E L I M I N A R Y
132
Am79C930
PCMCIA MEMORY WRITE ACCESS
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
t
AVWL
Address setup to
WE
↓
20
ns
t
AVWH
Address setup to
WE
↑
100
ns
t
WMAX
Write recovery time
(Address hold from
WE
↑
)
20
ns
t
ELWH
CE
setup to
WE
↑
140
ns
t
ELWL
CE
setup to
WE
↓
0
ns
t
GHEH
CE
hold from
OE
↑
(READ) or
CE
hold from
WE
↑
(WRITE)
20
ns
t
GHWL
OE
setup to
WE
↓
10
ns
t
WHGL
OE
hold from
WE
↑
10
ns
t
WLWH
WE
pulse width
120
ns
t
WLWTV
WAIT
valid from
WE
↓
35
ns
t
WTLWTH
WAIT
pulse width
Notes 1, 2
53 X T
CLKIN
ns
t
WTHWH
WE
hold from
WAIT
↑
0
ns
t
DVWH
Data setup to
WE
↑
60
ns
t
WMDX
Data hold from
WE
↑
30
ns
t
GHQZ
Data disabled from
OE
↑
Note 2
90
ns
t
WLQZ
Data disabled from
WE
↓
Note 2
90
ns
t
WHQNZ
Data enabled from
WE
↑
Note 2
5
ns
t
GLQNZ
Data enabled from
OE
↓
Note 2
5
ns
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
FLASH and SRAM wait states set at “3.”
1
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
4
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.