AMD Am79C930 - Manual (Page 88)

AMD P R E L I M I N A R Y
88 Am79C930
TIR mapping with SIR1 bit 2 (EIOW) set to “1” = Ex-
panded TIR window mode. Note that the setting EIOW = 1 is only allowed while operating in PCMCIA
mode. TIR uses 32 I/O addresses:
TIR SIR1[1:0] 80188 Core
Register (TAI Bank PCMCIA Address in
Number TIR Register Name Select) I/O Address Memory
0 Network Control XX* 0008h mem 400h
1 Network Status XX 0009h mem 401h
2 Serial Device XX 000Ah mem 402h
3 Fast Serial Port Control XX 000Bh mem 403h
4 Interrupt Register 1 XX 000Ch mem 404h
5 Interrupt Register 2 XX 000Dh mem 405h
6 Interrupt Mask 1 XX 000Eh mem 406h
7 Interrupt Mask 2 XX 000Fh mem 407h
8 Transmit Control XX 0010h mem 408h
9 Transmit Status XX 0011h mem 409h
10 TX FIFO Data XX 0012h mem 40Ah
11 Transmit Sequence Control XX 0013h mem 40Bh
12 Byte Counter LSB XX 0014h mem 40Ch
13 Byte Counter MSB XX 0015h mem 40Dh
14 Byte Counter Limit LSB XX 0016h mem 40Eh
15 Byte Counter Limit MSB XX 0017h mem 40Fh
16 Receiver Control XX 0018h mem 410h
17 Receiver Status XX 0019h mem 411h
18 RX FIFO Data XX 001Ah mem 412h
19 Antenna Slot XX 001Bh mem 413h
20 CRC32 Correct Count LSB XX 001Ch mem 414h
21 CRC32 Correct Count MSB XX 001Dh mem 415h
22 CRC8 Correct Count LSB XX 001Eh mem 416h
23 CRC8 Correct Count MSB XX 001Fh mem 417h
24 Configuration Index XX 0020h mem 418h
25 Configuration Data Port XX 0021h mem 419h
26 Antenna Diversity & A/D XX 0022h mem 41Ah
27 SAR XX 0023h mem 41Bh
28 RSSI Lower Limit XX 0024h mem 41Ch
29 USER Pin Data XX 0025h mem 41Dh
30 Dummy Register XX 0026h mem 41Eh
31 TEST Register XX 0027h mem 41Fh
*XX = Don’t care.