AMD Am79C930 - Manual (Page 133)

P R E L I M I N A R Y AMD
133 Am79C930
PCMCIA I/O READ ACCESS
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
t
AVIGL
Address setup to IORD ↓
70 ns
t
IGHAX
Address hold from IORD ↑
20 ns
t
RGLIGL
REG setup to IORD ↓
5 ns
t
IGHRGH
REG hold from IORD ↑ 0 ns
t
ELIGL
CE setup to IORD ↓
5 ns
t
IGHEH
CE hold from IORD ↑
20 ns
t
IGLIGH
IORD width 165 ns
t
IGLIAL
INPACK ↓
delay from IORD ↓
0 45 ns
t
IGHIAH
INPACK ↑ delay from IORD ↑ 45 ns
t
IGLWTL
WAIT ↓ delay from IORD ↓ 35 ns
t
WTLWTH
WAIT width Notes 1, 2 53 X T
CLKIN
ns
t
WTHQV
Data delay from WAIT ↑
0 ns
t
IGLQNZ
Data enabled from IORD ↓
Note 2 0 ns
t
IGLQV
Data delay from IORD ↓ 100 ns
t
IGHQX
Data hold from IORD ↑ 0 ns
t
IGHQZ
Data disabled from IORD ↑
Note 2 20 ns
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value Worst Case
0 FLASH and SRAM wait states set at “3.”
1 Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2 PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3 Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
4 After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5 After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6 After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7 At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.