AMD Am79C930 - Manual (Page 23)

Am79C930 23
P R E L I M I N A R Y
ISA PLUG AND PLAY PIN SUMMARY
No. of
Pins Pin Name Pin Function Pin Style
7 LA23–LA17 ISA upper address bus lines I
17 SA16–SA0 ISA lower address bus lines I
8 SD7–SD0 ISA data bus lines TS2
1 RESET RESET input I
1 MEMR
Memory Read—used to enable the output drivers of the Am79C930 device for
ISA bus memory read accesses
I
1 MEMW
Memory Write—used to indicate that the current ISA bus cycle is a memory
write access
I
1 AEN Address Enable—used to indicate that the current ISA bus I/O address is valid I
1 BALE
Bus Address Latch Enable—used to indicate that the ISA address lines are
valid
I
1 IOCHRDY I/O Channel Ready—used to delay the termination of the current ISA bus cycle TS2
1 IOR
I/O Read—this signal is asserted by the ISA host system whenever an I/O read
operation occurs
I
1 IOW
I/O Write—this signal is asserted by the ISA host system whenever an I/O write
operation occurs
I
6 IRQ4, 5, 9, 10, 11, 12
Interrupt Request—this line is asserted when the Am79C930 device needs
servicing from the software
PTS3/OD2
1 RFRSH Refresh—indicates that the current ISA bus cycle is a refresh operation I
1 PCMCIA PCMCIA mode—selects PCMCIA or ISA Plug and Play mode I
1 PWRDWN Powerdown—indicates that device is in the power down mode TP1
17 MA16–0
Memory Address Bus—these lines are used to address locations in the Flash
device, the SRAM device, and an extra peripheral device that are contained
within an Am79C930-based design
TP1
8 MD7–0
Memory Data Bus—these lines are used to write and read data to/from Flash,
SRAM, and/or an extra peripheral device within an Am79C930-based design
TS1
1 FCE
Flash Chip Enable—this signal becomes asserted when the Flash device has
been addressed by either the 80188 core of the Am79C930 device or by the
software through the PCMCIA interface
TP1
1 SCE
SRAM Chip Enable—this signal becomes asserted when the SRAM device
has been addressed by either the 80188 core of the Am79C930 device or by
the software through the PCMCIA interface
TP1
1 XCE
eXtra Chip Enable—this signal becomes asserted when the extra peripheral
device has been addressed by the 80188 core of the Am79C930 device (XCE
is not accessible through the system interface)
TP1
1 MOE
Memory Output Enable—this signal becomes asserted during reads of devices
located on the memory interface bus
TP1
1 MWE
Memory Write Enable—this signal becomes asserted during writes to devices
located on the memory interface bus
TP1
1 TCK Test Clock—this is the clock signal for IEEE 1149.1 testing I
1 TDI Test Data In—this is the data input signal for IEEE 1149.1 testing I
1 TDO Test Data Out—this is the data output signal for IEEE 1149.1 testing TS1
1 TMS Test Mode Select—this is the test mode select for IEEE 1149.1 testing I
1 TRST Test Reset—this is the reset signal for IEEE 1149.1 testing I
1 TEST
Test pin—when asserted, this pin places the Am79C930 device into a
non-IEEE 1149.1 test mode
I
1 CLKIN
Clock input to drive BIU, 80188 core, and TAI, supplying network data rate
information
I
2 PMX1–2 Power Management Xtal—32-kHz Xtal input for sleep timer reference I/XO