PNI ASIC - Manual (Page 8)

PNI ASIC
Host Processor Interface
SPI Port Line Descriptions
MOSI – Master Out Slave In
The data sent from the master to the PNI ASIC. Data is transferred most significant bit first. The MOSI line
will accept data once the SPI is enabled by taking SSNOT low. Valid data must be presented at least 100
nS before the rising edge of the clock, and remain valid for 100 nS after the edge. New data may be
presented to the MOSI pin on the falling edge of SCLK
SSNOT – Slave Select
Selects the PNI ASIC as the operating slave device. The SSNOT line must be low prior to data transfer and
must stay low during the entire transfer. Once the command byte is received by the PNI ASIC, and the PNI
ASIC begins to execute the command, the SSNOT line can be deselected until the next SPI transfer.
SCLK – Serial Clock
Used to synchronize both the data in and out through the MISO and MOSI lines. SCLK is generated by a
master device. SCLK should be 1 MHz or less. The PNI ASIC is configured to run as a slave device,
making it an input. One byte of data is exchanged over eight clock cycles. Data is captured by the master
device on the rising edge of SCLK. Data is shifted out and presented to the PNI ASIC on the MOSI pin on
the falling edge of SCLK.
MISO – Master In Slave Out
The data sent from the PNI ASIC to the master. Data is transferred most significant bit first. The MISO line
is placed in a high impedance state if the slave is not selected (SSNOT = 1).
PNI Corporation 133 Aviation Blvd., Suite 101, Santa Rosa, CA 95403‐1084 USA;, Fax: (707) 566‐2261
For the most current specifications, please visit our website at:
www.pnicorp.com
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