Advantech PCM-9588 - Manual (Page 35)

25 PCM-9588 User Manual
Chapter 3
B
IOS Operation
3.2.4 Advanced Chipset Features
! DRAM Timing Selectable [By SPD]
This item enables users to set the optimal timings for items 2 through 5, system
default setting of "By SPD" to follow the SPD information and ensure the system
running in stable and optimal performance.
! CAS Latency Time [Auto]
This item enables users to set the timing delay in clock cycles before SDRAM
start a read command after receiving it.
! DRAM RAS# to CAS# Delay [Auto]
This item enables users to set the timing of the transition from RAS (row
address strobe) to CAS (column address strobe) as both rows and column are
separately addressed shortly after DRAM is refreshed.
! DRAM RAS# Precharge [Auto]
This item enables users to set the DRAM RAS# precharge timing, system
default is setting to "Auto" to reference the data from SPD ROM.
! Precharge delay (tRAS) [Auto]
This item allows user to adjust memory precharge time
! System Memory Frequency [Auto]
This item allows user to adjust memory frequency to improvement performance.
! SLP_S4# Assertion Width [4 to 5 Sec]
This item allow user to set the SLP_S4# Assertion Width.
! System BIOS Cacheable [Enabled]
This item allows the system BIOS to be cached to allow faster execution and
better performance.
! Video BIOS Cacheable [Disabled]
Note! This "Advanced Chipset Features" option controls the configuration of
the board's chipset; items on this page depend on the chipset installed.
It is strongly recommended only technical users make changes to the
default settings.