ARM AMBA NIC-301 - Manual (Page 45)

Programmers Model
ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 3-7
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3.2.2 Register blocks
This section contains the following subsections:
•
Address region control
• Peripheral ID registers on page 3-8.
Address region control
Table 3-4 shows the address region control registers.
0x040 RW 4 a wr_tidemark Reserved.
0x044 RW 2 - ahb_cntl This register is available for AHB only. You can configure the register bits
as follows:
0
decerr_en .
1
force_incr
.
See AHB master interfaces on page 2-9.
0x100 - - - - Reserved.
0x104 - - - - Reserved.
0x108 RW 2 0 fn_mod_iss Issuing functionality modification register. This register is only available
if you are upsizing or downsizing, or you have a FIFO for any of the
channels. This register sets the block issuing capability to be forced to one
transaction. You can configure the register bits as follows:
0
Read issuing, read_iss_override .
1 Write issuing,
write_iss_override
.
a. The reset value is initialized to the tidemark value that you set in the configuration GUI in AMBA Designer (ADR-301).
Table 3-3 Registers for each AMIB (continued)
Address
offset
Type Width
Reset
value
Name Description
Table 3-4 Address region control registers
Address
offset
Type Width
Reset
value
Name Description
0x0 WO 8 0x00 Remap Remap register. Up to eight global remap states are available.
0x4
-
0xC
WO - - - Reserved.
0x10 WO 1 - 16 - security0 Slave 0 security setting. This consists of one bit for non-virtual slaves,
and up to 16 bits for virtual or APB master interfaces, and you can
configure the register bits as follows:
0
Secure.
1 Non-secure.
Note
For virtual or APB master interfaces with 16 security setting bits, each
bit position maps onto the region number. For example, the security1[5]
bit is the security setting for the address region for master interface node
number 1, region 5.