ARM AMBA NIC-301 - Manual (Page 52)

Glossary
ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. Glossary-3
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Active write transaction
A transaction for which the write address or leading write data has transferred, but
the write response has not yet transferred.
Completed transfer
A transfer for which the xVALID/xREADY handshake is complete.
Payload The non-handshake signals in a transfer.
Transaction An entire burst of transfers, comprising an address, one or more data transfers and
a response transfer (writes only).
Transmit An initiator driving the payload and asserting the relevant xVALID signal.
Transfer A single exchange of information. That is, with one xVALID/xREADY
handshake.
The following AXI terms are MI attributes. To obtain optimum performance, they must be
specified for all components with an AXI MI:
Combined issuing capability
The maximum number of active transactions that a master interface can generate.
It is specified for master interfaces that use combined storage for active write and
read transactions. If not specified then it is assumed to be equal to the sum of the
write and read issuing capabilities.
Read ID capability
The maximum number of different ARID values that an MI can generate for all
active read transactions at any one time.
Read ID width
The number of bits in the ARID bus.
Read issuing capability
The maximum number of active read transactions that an MI can generate.
Write ID capability
The maximum number of different AWID values that an MI can generate for all
active write transactions at any one time.
Write ID width
The number of bits in the AWID and WID buses.
Write interleave capability
The number of active write transactions for which the MI is capable of
transmitting data. This is counted from the earliest transaction.
Write issuing capability
The maximum number of active write transactions that an MI can generate.