ARM AMBA NIC-301 User Manual

Page 53

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Glossary

ARM DDI 0397G

Copyright © 2006-2010 ARM. All rights reserved.

Glossary-4

ID031010

Non-Confidential

The following AXI terms are SI attributes. To obtain optimum performance, they must be
specified for all components with an AXI SI:

Combined acceptance capability

The maximum number of active transactions that a slave interface can accept. It
is specified for slave interfaces that use combined storage for active write and
read transactions. If not specified then it is assumed to be equal to the sum of the
write and read acceptance capabilities.

Read acceptance capability

The maximum number of active read transactions that an SI can accept.

Read data reordering depth

The number of active read transactions for which an SI can transmit data. This is
counted from the earliest transaction.

Write acceptance capability

The maximum number of active write transactions that an SI can accept.

Write interleave depth

The number of active write transactions for which the SI can receive data. This is
counted from the earliest transaction.

Beat

Alternative word for an individual transfer within a burst. For example, an INCR4 burst
comprises four beats.

See also Burst.

Burst

A group of transfers to consecutive addresses. Because the addresses are consecutive, there is
no requirement to supply an address for any of the transfers after the first one. This increases
the speed at which the group of transfers can occur. Bursts over AMBA are controlled using
signals to indicate the length of the burst and how the addresses are incremented.

See also Beat.

Cache

A block of on-chip or off-chip fast access memory locations, situated between the processor and
main memory, used for storing and retrieving copies of often used instructions and/or data. This
is done to greatly increase the average speed of memory accesses and so improve processor
performance.

Halfword

A 16-bit data item.

Multi-layer

An interconnect scheme similar to a cross-bar switch. Each master on the interconnect has a
direct link to each slave, The link is not shared with other masters. This enables each master to
process transfers in parallel with other masters. Contention only occurs in a multi-layer
interconnect at a payload destination, typically the slave.

Processor

A processor is the circuitry in a computer system required to process data using the computer
instructions. It is an abbreviation of microprocessor. A clock source, power supplies, and main
memory are also required to create a minimum complete working computer system.

Region

A partition of instruction or data memory space.

Remapping

Changing the address of physical memory or devices after the application has started executing.
This is typically done to permit RAM to replace ROM when the initialization has been
completed.

Unaligned

A data item stored at an address that is not divisible by the number of bytes that defines the data
size is said to be unaligned. For example, a word stored at an address that is not divisible by four.

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