Achronix ACE Version 5.0 User Manual
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Chapter 3. Concepts
Resynthesis Strategy Details (within Advanced Design Preparation)
ACE tries to improve QOR by resynthesizing portions of the design during the Run Prepare
The Resynthesis Timing Rules (Rewrite Rule 1, Rewrite Rule 2, Move Flop-flop Reset, and Loop Speed-
up
) only control the optimizations performed when Resyntheses Mode is set to Optimize for Timing (i.e.
when the implementation option
synthesis remap
is set to
timing
). The optimizations can be broadly
classified into two categories: Rewrite and Loop Speedup.
Rewrite:
Rewrite attempts to reduce the number of LUTs in series. In order to do so, it applies the
following two transformations, called Rule 1 and Rule 2.
Figure 3.69: Rewrite Rule 1
Figure 3.70: Rewrite Rule 2
Note that these transformations are not always feasible. Rewrite looks at the LUT programs and the number
of used inputs to determine where to apply these rules. When optimizing for timing, rewrite works on
critical loops (and the long leg of reconvergent paths if the target device is an asynchronous FPGA). When
optimizing for area, rewrite attempts to apply Rule 1 on all LUTs in the design.
Loop Speedup:
While the Rewrite Rules look at only pairs of LUTs, loop speedup looks at complete loops
and remaps them to improve performance. In general, this improves QOR on loop-dominated designs.
The extent of improvement depends mainly on the overlap among loops. Loop speedup performs better
if the loops are disjoint (i.e., they do not share logic). Furthermore, since loop speedup does not optimize
carry chains, it may not improve performance if the critical loop is solely comprised of carry chains. Loop
speedup does nothing to reconvergent paths; however, while optimizing a loop, it may affect reconvergent
paths that overlap with the loop.
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