Achronix ACE Version 5.0 User Manual
Page 90
Editors
Chapter 3. Concepts
Power Management Page
This page contains all the options for PCIe power management.
Figure 3.44: PCIe IP Editor Power Management Page
PCIe Editor Power Management Page Options
Option
Description
NTFS (hex)
Number of NFTS sets to request when exiting L0s. This is the NFTS value
transmitted in TS1 and TS2 Ordered Sets during training.
L0s Tx Entry Time
(hex)
Number of nanoseconds of idle time to wait before entering L0s TX. Idle time
is defined as no TLP or DLLP transmission pending or actively being
transmitted. By PCIe Specification, the value programmed should be ⇐ 7 uS
(0x1B58). Too low a value risks wasting link bandwidth due to L0s entry/exit
latencies. Too high a value will reduce L0s power savings.
Endpoint L0s
Acceptable Latency
From PCI Express Base Specification, Rev 2.1 section 7.8.3: Acceptable total
latency that an Endpoint can withstand due to the transition from L0s state to
the L0 state. It is essentially an indirect measure of the Endpoint’s internal
buffering.
L0s Exit Latency
Length of time required to complete transition from L0s to L0
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