Achronix ACE Version 5.0 User Manual
Page 37
Editors
Chapter 3. Concepts
Clock Enable Priority
Y
The Clock Enable Priority defines the priority
of the outregcea clock enable input relative to
the rstrega reset input during an assertion of
the rstrega signal on the output register of
Port A. The value rstreg allows the Port A
output register to be set/reset at the next
active edge of the Port A clock without
requiring a specific value on the outregcea
output register clock enable input. The value
regce
requires that the outregcea output
register clock enable input is high for the
output register set/reset operation to occur at
the next active edge of the Port A clock.
Output Register Reset
Active-High
Y
When this is enabled, the output register has
an active-high synchronous reset. Otherwise,
the output register reset will be active-low.
Port B
Port B Configuration
Y
BRAMs can be configured for read, write, or
read/write capability independently on both
Port A and Port B sides of the BRAM.
Data Width
Y
Port A side write and read port data width.
We currently only support Port A data width
being a ratio of 1:2n or 2n:1 with Port B data
width. The max ratio is 1:32 or 32:1. This
field imposes limitations on the Port B side
data width and address depth.
Address Depth
Port A side address depth is the total number
of data words accessible via Port A. This field
imposes limitations on the Port B side data
width and address depth. The Port B data
width must be a valid integer ratio of the
Port A data width.
Write Mode
Y
The write mode can be set to No Change in
order to keep the read port value constant
until the next read. It can be set to Write First
to allow the write data to be seen on the read
port before the next read.
Clock Polarity
Y
The write port clock polarity can be set to use
either rising edge assignment or falling edge
assignment.
Port Enable Active-High
Y
When this is enabled, the port enable peb is
active-high. Otherwise, the port enable will
be active-low.
Output Latch Reset Active-High
Y
When this is enabled, the output latch has an
active-high synchronous reset. Otherwise,
the output latch reset will be active-low.
Output Register Enabled
Y
When the Output Register is enabled, there is
an additional cycle of latency for each read
operation.
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UG001 Rev. 5.0 - 5th December 2012