Achronix Speedster22i Snapshot - Manual (Page 11)

users_logic_block_instance: users_logic
port map ( clk => usr_clk,
rstn => rstn,
data_out_from_block => monitor_ch_to_monitor ,
data_for_trigger => trigger_ch_to_trigger,
snapshot_arm => arm,
stimuli => stimuli);
----- END VHDL EXAMPLE ---
Snap_shot_core
36
Snapshot_top
User Logic
36
tck
trstn
tms
tdi
tdo
usr_clk
Monitor_ch
trigger_ch
36
Arm
Stimuli
rstn_out
Figure 4: Block diagram of Snapshot macro connection to user’s logic
After incorporating the Snapshot macro into the design, the user will be able to synthesize
the design with the Synplify-Pro or Precision synthesis tool. After synthesis, the generated
netlist can be imported into ACE (Achronix CAD Environment), to generate the FPGA
programming file.
Note: To implement the Snapshot macro, the user needs to include timing and placement
constraints via an SDC and PDC file. Below are the Snapshot-specific constraints:
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