Kontron CG2200 Carrier Grade Server - Manual (Page 32)

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Kontron CG2200 Carrier Grade Server Installation and Maintenance Guide
The S2600CO server board memory is implemented according to the following rules
•
DIMMs are organized into physical slots on DDR3 memory channels that belong to processor
sockets.
•
The memory channels from processor socket 1 are identified as Channel A, B, C, and D.
The memory channels from processor socket 2 are identified as Channel E, F, G, and H.
•
Each memory slot on the server board is identified by channel and slot number within the
channel.
For example, DIMM_A1 is the first slot on Channel A on processor 1; DIMM_E1 is the first
DIMM socket on Channel E on processor 2.
•
The memory slots associated with a given processor are unavailable if the given processor
socket is not populated.
•
A processor can be installed without populating the associated memory slots, provided the
other processor is installed with associated memory. In this case, the memory is shared by
the processors. However, the platform suffers performance degradation and latency because
of the remote memory accesses.
•
Processor sockets are self-contained and autonomous. However, all memory subsystem
support (i.e., Memory RAS, Error Management, etc.) in the BIOS setup is applied commonly
across processor sockets.
•
The blue memory slots on the server board identify the first memory slot for each memory
channel.
For more information about population considerations, see Section 3.2.2.2 “Memory Slot Identification
and Population Rules” in the Intel® Server Board S2600CO Family TPS.
3.3.3 Publishing System Memory
The BIOS displays the “Total Memory” of the system during POST if “Display Logo” is disabled in the
BIOS setup. This is the total size of memory discovered by the BIOS during POST and it is the sum of the
individual installed DDR3 DIMMs in the system. The BIOS provides the total memory of the system in the
main page of the BIOS setup.
The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term “Effective Memory”
refers to the total size of all DDR3 DIMMs that are active (not disabled) and not used as redundant units.
3.3.4 Integrated Memory Controller Operating Modes.
The following operating modes are supported:
•
Independent channel mode
•
Lockstep channel mode
•
Mirror mode
For detailed information about these different operating modes, see Section 3.2.2.4, “Integrated Memory
Controller Operating Modes” in the Intel® Server Board S2600CO Family TPS.
3.3.5 Memory RAS
The server board supports the following memory RAS modes:
•
Single Device Data Correction (SDDC)
•
Error Correction Code (ECC) memory
•
Demand scrubbing for ECC memory
•
Patrol scrubbing for ECC memory
•
Rank sparing mode
•
Mirrored channel mode
•
Lockstep channel mode