Solvline Eddy DKV2.1.0.3 - Manual (Page 45)

Chapter 3. Development
Environment
45
2.5.2.4. PIOB and PIOC (Peripheral I/O Controller B/C)
S4M
Pin No
(124)
Name
S4M-JIG
Pin HDR
(46*2)
S4M-DK
Pin HDR
(46*2)
Description
57 PB0 J5 pin11 J7 pin11
Peripheral A : SPI1_MISO
SPI1(Serial Peripheral Interface)
Master In Slave Out
Peripheral B : TIOA3 Timer Counter ch3 I/O Line A
58 PB1 J5 pin12 J7 pin12
Peripheral A : SPI1_MOSI
SPI1(Serial Peripheral Interface)
Master Out Slave In
Peripheral B : TIOB3 Timer Counter ch3 I/O Line B
59 PB2 J5 pin13 J7 pin13 Peripheral A : SPI1_SPCK
SPI1(Serial Peripheral Interface) Serial
Clock
60 PB3 J5 pin14 J7 pin14
Peripheral A : SPI1_NPCS0
SPI1(Serial Peripheral Interface)
Peripheral Chip Select 0
Peripheral B : TIOA5 Timer Counter ch5 I/O Line A
61 PB12 J5 pin17 J7 pin17 Peripheral A : TXD5 USART5 Transmit Data
64 PB13 J5 pin18 J7 pin18 Peripheral A : RXD5 USART5 Receive Data
65 PB16 J5 pin119 J7 pin119
Peripheral A : TK0 SSC Transmit Clock
Peripheral B : TCLK3 Timer Counter ch3 External CLK IN
66 PB17 J5 pin20 J7 pin20
Peripheral A : TF0 SSC Transmit Frame Sync
Peripheral B : TCLK4 Timer Counter ch4 External CLK IN
67 PB18 J5 pin21 J7 pin21
Peripheral A : TD0 SSC Transmit Data
Peripheral B : TIOB4 Timer Counter ch4 I/O Line B
68 PB19 J5 pin22 J7 pin22
Peripheral A : RD0 SSC Receive Data
Peripheral B : TIOB5 Timer Counter ch5 I/O Line B
71 PB20 J5 pin23 J7 pin23 Peripheral A : RK0 SSC Receive Clock
72 PB21 J5 pin24 J7 pin24 Peripheral A : RF0 SSC Receive Frame Sync
73 PB30 J5 pin25 J7 pin25 Peripheral A : PCK0 Programmable Clock Output 0
75 PC0 J5 pin27 J7 pin27 Peripheral A : AD0 Analog to Digital Converter Input Ch0
76 PB31 J5 pin26 J7 pin26 Peripheral A : PCK1 Programmable Clock Output 1