Service pin, Clock pins, Software controlled reset – Echelon FTXL Hardware User Manual

Page 35: Watchdog timer, Lvi considerations, Reset processes and timing

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FTXL Hardware Guide

27

Software Controlled Reset

When the CPU watchdog timer expires, or a software command to reset occurs,

the RESET~ pin is asserted (pulled low) for 256 CLK1 clock cycles. The RESET~

pin external capacitor (100 ≤ C

E

≤ 1000 pF) begins charging and provides the

required duration of reset.

Watchdog Timer

The FTXL Transceiver is protected against malfunctioning software or memory
faults by three watchdog timers, one for each processor that makes up the

Neuron core. If the system software fails to reset these timers periodically, the
entire FTXL Transceiver automatically resets. The watchdog period is

approximately 840 ms when running at 10 MHz, approximately 210 ms at a 40

MHz input clock rate, and scales inversely with the input clock rate.

LVI Considerations

The FTXL Transceiver includes an internal LVI to ensure that it only operates

above the minimum voltage threshold. See the

FT 3120 and FT 3150 Smart

Transceiver Datasheet

for LVI trip points.

Reset Processes and Timing

During the reset period, the I/O pins are in a high-impedance state. The data

lines are undetermined but driven high or low, so that they do not float and draw

excess current. The SERVICE~ pin is high impedance during reset. After the
RESET~ pin is released, the FTXL Transceiver performs hardware and firmware

initialization before communicating with the host processor.

Service Pin

The service pin (pin 5) function for an FTXL device is controlled by the host
processor. The SERVICE~ pin on the FTXL Transceiver is not used.

Clock Pins

The FTXL Transceiver operates with an input clock of 5, 10, 20, or 40 MHz. The

FTXL Transceiver divides the input clock by a factor of two to provide a
symmetrical on-chip system clock. The input clock can be generated either by an

external free-running oscillator or by the on-chip oscillator in the FTXL

Transceiver using an external parallel-mode resonant crystal.

The accuracy of the input clock frequency of the FTXL Transceiver must be ±200

ppm or better; this requirement can be met with a suitable crystal, but cannot
generally be met with a ceramic resonator.
The FTXL Transceiver includes an oscillator that can be used to generate an

input clock using an external crystal. For 5 MHz, 10 MHz, and 20 MHz, either
an external clock source or the on-chip crystal oscillator can be used. For 40 MHz

operation, an external oscillator must be used.

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