Echelon FTXL Hardware - Manual (Page 56)

48 FPGA Design for the FTXL Transceiver
• chipselect: Select signal to enable access to the reset pin
• write_n: Write-select signal to write to the reset pin
• writedata: Data signal to the reset pin
• readdata: Data signal from the reset pin
• bidir_port: Bidirectional signal for the reset pin
Phase-Locked Loop
If your FPGA design includes a phase-locked loop (PLL) component, be sure to
connect one of its clock-out signals to the CLK_IN signal of the FTXL parallel I/O
transceiver interface component. The CLK_IN signal requires the following
characteristics for the PLL clock-out signal:
• Ratio: 1/1
• Phase shift: 0
• Clock duty cycle: 50%
If your FPGA design does not include a PLL component, be sure to connect the
CLK_IN signal to an external oscillator with the same characteristics and the
same clock speed as the Nios II processor clock.
DBC2C20 Components
Although the reference designs that are provided with the DBC2C20
development board include several SOPC Builder components, the FTXL
Developer’s Kit reference design uses only one of the SOPC Builder components
for the DBC2C20 development board: the DBC2C20 SRAM interface. This
component is installed to the [ NiosEDS ]\components\DBC2C20_sram_interface
directory.
You do not need to install any of the SOPC Builder components for the DBC2C20
development board from the CD-ROM that accompanies the DBC2C20
development board.
Your FTXL device can include any appropriate SRAM components, but a design
that uses the DBC2C20 development board must use the DBC2C20 SRAM
interface component.
Timers
The FTXL Developer’s Kit reference design includes a system timer (a 1 ms
timer) and a high-resolution timer (a 1 μs timer). The high-resolution timer is
not used by the FTXL software, but is included for applications that require a
timer with higher resolution than the system clock.
External Memory
The FTXL Developer’s Kit reference design includes the following external
memory:
• 1 MB SRAM