Echelon FTXL Hardware - Manual (Page 68)

60 Working with the Altera Development Environments
Modifying the Quartus II Design
Before you begin, ensure that the Quartus II global library or project library
search path includes the FTXL components; see Setting Component Search Paths
on page 56.
After you generate the SOPC Builder design, you can update your Quartus II
design, including updating the symbol block for the Nios II processor in the block
design file (*.bdf) for the project. The updated Nios II block symbol should
include the signals shown in Figure 24 and Figure 25.
Figure 24. FTXL Signals within the Nios II Processor
Figure 25. FTXL Parallel I/O Signals within the Nios II Processor
Within the block design file (*.bdf) for the project, you need to add a symbol block
for the FTXL Parallel Interface Delay component:
1. Right-click the canvas and select Insert → Symbol to open the Symbol
dialog.
2. In the Symbol dialog, expand the [ Altera ]\nios2eds\components\ftxl
folder. If this folder does not display, be sure that you have added the
FTXL components to the SOPC Builder library path, as described in
Setting Component Search Paths on page 56.
3. Select FTXL_PIO_Delay from the [ Altera ]\nios2eds\components\ftxl
folder. Figure 18 on page 42 shows this component’s block symbol.
4. Click OK to close the Symbol dialog and to add the symbol to the canvas.
After you add the FTXL_PIO_Delay symbol to the canvas, you need to connect its
signals to the FTXL Parallel I/O signals within the Nios II processor:
• Connect CS_IN to CS_to_the_FTXL_PIO_inst
• Connect AO_IN to address_to_the_FTXL_PIO_inst
• Connect RW_IN to RW_to_the_FTXL_PIO_inst
• Connect RESET_IN to reset_n
In addition, you need to connect CLK_IN to the system clock signal for the Nios
II processor (for example, the clock output of a PLL). Figure 26 on page 61 shows
the main connections for the FTXL_PIO_Delay component.