Echelon FTXL Hardware - Manual (Page 70)

62 Working with the Altera Development Environments
6. Load the modified hardware design for the Nios II processor into the
FPGA device, as described in Loading the Application Image into the
FPGA Device .
Loading the Application Image into the FPGA
Device
You can choose to load the hardware and software images into the FPGA device’s
RAM at the same time, or you can choose to load them separately. To load both
images at the same time, or to load the images into the FTXL device’s flash
memory, use the Nios IDE; see the FTXL User’s Guide for more information.
To load the hardware image for the Nios II processor into the FPGA device:
1. Ensure that the FPGA device is powered on and that the USB-Blaster
download cable (or similar programming device) is connected to it.
2. Start the Quartus II software.
3. Select File → Open Project to display the Open Project window.
4. In the Open Project window, select the Quartus Project File (*.qpf) for the
project, and click Open to add the project file to the Project Navigator.
5. Select Tools → Programmer to open the Chain Description File view for
the project.
6. Ensure that the USB-Blaster download cable (or similar programming
device) is defined in the Chain Description File for the project.
If you have not defined the USB-Blaster download cable in the Chain
Description File for the project, click Hardware Setup. See Using a
Device Programmer for the FPGA Device on page 55 for more information
about setting up the USB-Blaster download cable.
7. Verify that the SRAM Object File (*.sof) for the project is already listed in
the Chain Description File view for the project.
If the SRAM Object File (*.sof) for the project is not listed in the Chain
Description File view for the project, click Add File to open the Select
Programming File dialog. From the Select Programming File dialog,
select the SRAM Object File (*.sof) for the project, and click Open to add
the file to the Chain Description File view for the project.
8. Verify that the Program/Configure checkbox is selected for the hardware
design file.
9. Click Start to load the hardware design into the FPGA device.
10. After the Quartus II software has finished loading the hardware image
into the FPGA device, perform a reset of the FPGA device.
11. Select File → Exit if you want to close the Quartus II software window.