Overview, Overview -1 – Altera MAX 10 JTAG User Manual

Page 3

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Overview

1

2015.05.04

UG-M10JTAG

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MAX

®

10 devices support the IEEE Std.1149.1 (JTAG) boundary-scan testing (BST).

When you perform BST, you can test pin connections without using physical test probes and capture

functional data during normal operation. The boundary-scan cells (BSCs) in a device can force signals

onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the BSCs.

Captured data is serially shifted out and externally compared to expected results.
Note: You can perform BST on MAX 10 devices before, after, and during configuration.

Related Information

MAX 10 FPGA Configuration User Guide

Provides more information about JTAG in-system programming.

JTAG BST Architecture

on page 2-1

JTAG Boundary-Scan Register

on page 2-2

JTAG BST Operation Control

on page 3-1

I/O Voltage Support in the JTAG Chain

on page 4-1

Enabling and Disabling JTAG BST Circuitry

on page 5-1

Guidelines for JTAG BST

on page 6-1

Boundary-Scan Description Language Support

on page 7-1

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