Altera Avalon Tri-State Conduit Components - Manual (Page 15)

Chapter 3: Tri-State Conduit Pin Sharer 3–3
Arbitration
May 2011 Altera Corporation Avalon Tri-State Conduit Components User Guide
Preliminary
Arbitration
Each Avalon-TC master and slave pair includes separate request and grant signals.
Arbitration logic in the Tri-State Conduit Pin Sharer grants requesting masters in
round-robin order. The meaning of the
request signal depends on the state of the
grant signal. The request / grant algorithm has the following dependency on the
current state:
1. When request is asserted and grant is deasserted, request is requesting access for
the current cycle.
2. When request is asserted and grant is asserted, request is requesting access for
the next cycle; consequently, request should be deasserted on the final cycle of an
access.
Because request is deasserted in the final cycle of a bus access, it can be reasserted
immediately following the final cycle of a transfer, making both rearbitration and
continuous bus access possible if no other masters are requesting access. After it is
asserted, request must remain asserted until granted; consequently, the shortest bus
access is two cycles.
The grant signal is asserted in response to the request signal and remains asserted
until one cycle following the deassertion of request . The design of the Avalon-TC
interface does not allow a default Avalon-TC master to be granted bus access when no
masters are requesting.
Figure 3–4 illustrates arbitration timing for the Tri-State Conduit Pin Sharer. As this
figure illustrates, a device can drive or receive valid data in the granted cycle.
Figure 3–4 shows the following sequence of events:
1. In cycle 1, the tri-state conduit master asserts grant. The granted slave drives valid
data in cycles 1 and 2.
2. In cycle 4, the tri-state conduit master asserts grant. The granted slave drives valid
data in cycles 4–7.
3. In cycle 8, the tri-state conduit master asserts grant. The granted slave drives valid
data in cycles 8–16.
4. Cycle 3 is the only cycle that does not contain valid data.
Figure 3–4. Arbitration Timing
clk
request
grant
data_out[31:0] 0 a b c d e f 10 11 12 13 14 15 16 17
1 3 6 2 7 4 5 8 10 13 9 14 11 12 16 17 15
.