Altera Avalon Tri-State Conduit Components - Manual (Page 8)

2–2 Chapter 2: Generic Tri-State Controller
Parameters
Avalon Tri-State Conduit Components User Guide May 2011 Altera Corporation
Preliminary
Parameters
The Generic Tri-State Controller provides preset configurations for many commonly
used external devices. If you select one of the preset configurations, all of the
parameters are automatically assigned the correct values. Many preset configurations
are available, including presets for all of the following devices:
■ Legacy AMD 29LV065D Flash
■ AMD 29LV128M Flash with Legacy SDK support
■ Intel 128P30 Flash
■ Intel 256P30 Flash
■ SST39VF20090 Flash
■ Flash Memory Interface (CFI)
■ ISSI IS61LPS25636A-200TQL1 SSRAM
■ Cypress CY7C1380C SSRAM
■ IDT71V416 SRAM
■ LAN91C111 Interface
■ C8900 Interface (Ethernet)
You can use the parameter editor to specify the required settings for other external
devices. The appropriate values for these parameters are typically listed in the
vendor’s data sheet for the device.
Table 2–1 describes the parameters available on the Signal Selection tab of the
parameter editor for the Generic Tri-State Controller.
Table 2–1. Signal Selection Parameters
Parameter Value Description
Address Width 1–30 Specifies the width of the address signal.
Data Width
8,16,32,64,128,
256,512,1024
Specifies the width of the data signal.
Byteenable Width
1,2,4,8,16,
32,64,128
Specifies the width of the byteenable signal.
Bytes per word 1-128 Specifies the number of bytes per word.
readdata On/Off
Enables or disables the readdata signal which is driven from the external device
to the Generic Tri-State Controller in response to a read transfer.
writedata On/Off
Enables or disables the writedata signal which is driven from the Generic
Tri-state Controller to the external device during writes transfers.
read On/Off Enables or disables the read signal. If present readdata is required.
write On/Off Enables or disables the write signal. If present writedata is required.
begintransfer On/Off
Enables or disables the begintransfer signal, which is asserted during the
first cycle of any transfer regardless of the value of the waitrequest signal.