Altera CIC MegaCore Function - Manual (Page 19)

processing chain. This strategy can lead to full utilization of the resources and represents the most
efficient hardware implementation.
Figure 3-3: Multiple Input Single Output Architecture For Four Channels
The symbols A, B, C, D are multiplexed into one output A, B, C, D
D D D
(A, C)
(B, D)
(A, B, C, D)
3
3
I I I
I I I
D D D
The sampling frequency of the input data only allows time multiplexes of two channels per bus.
Therefore, you must configure the CIC filter with two input interfaces. For two interfaces, the rate change
factor must also be at least two to exploit this architecture. The CIC support up to 1,024 channels by using
multiple input interfaces in this way.
Note: The CIC applies the MISO architecture when you select a decimation filter and the number of
interfaces is greater than one.
Single Input Multiple Output (SIMO)
With single input multiple output (SIMO), all the channel signals presented for filtering come from a
single input interface.
Like the MISO, you can share the low sampling rate differentiator section among more channels than the
higher sampling frequency integrator sections. Therefore, this architecture features a single instance of the
differentiator section and multiple parallel instances of the integrator sections.
After processing by the differentiator section, the CIC splits the channel signals into multiple parallel
sections for processing in a high sampling frequency by the integrator sections.
UG-CIC
2014.12.15
Single Input Multiple Output (SIMO) 3-3
CIC IP Core Functional Description Altera Corporation
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