Altera CIC MegaCore Function - Manual (Page 25)

Parameter Value Description
Differentiator data
storage
Logic Element,
Memory
Selects whether to implement the differentiator data
storage as logic elements or memory. The Memory
option is available for differentiator data storage
when the product of the Differential delay, Number
of channels per interface and Number of interfaces
is greater than 4.
RAM type of
differentiator data
storage
AUTO, M9K, M10K,
M20K, M144K,
MLAB
When you select Memory, you can select the RAM
type for differentiator data storage. The options
available depend on the target device family. When
AUTO is selected, the Quartus II software automati‐
cally selects the optimum RAM type for the currently
selected device family.
Pipeline stages per
integrator
— Enter the pipeline stages per integrator. This option is
available when the Number of channels per interface
is greater than or equal to 2 (or greater than or equal
to 6, when you select the Memory option for
integrator data storage).
Use this option for multichannel designs that have
large input bit width and require high f
MAX
, but not
for designs targeting Cyclone devices.
Pipeline stages per
integrator
1 to 4 Specifies the number of pipeline stages used by each
integrator. Adding additional integrators can
improve f
MAX
but increases the resource utilization.
The maximum number of pipeline stages depends on
the number of channels and whether you select
Memory or Logic Cells for integrator data storage.
For Memory, the maximum number of pipeline
stages equals the number of channels minus 5. For
Logic Cells, the maximum number of pipeline stages
equals the number of channels.
CIC IP Core Interfaces and Signals
Table 3-3: Avalon-ST Interface Parameters
All parameters not explicitly listed have undefined values.
Parameter Name Value
READY_LATENCY
0
BITS_PER_SYMBOL
Data width
UG-CIC
2014.12.15
CIC IP Core Interfaces and Signals 3-9
CIC IP Core Functional Description Altera Corporation
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