Altera Double Data Rate I/O - Manual (Page 16)

This design implements the same divider as that in Design Example 1, but the functionality of the
ALTDDIO_IN
and
ALTDDIO_OUT
modules is implemented in a single megafunction, ALTDDIO_BIDIR.
The bidirectional pins
DDR_BIDIR8[7..0]
receive data at double the clock rate. The
DDRBIDIR8_OUT_H[7..0]
signals are the numerator and the
DDRBIDIR8_OUT_L[7..0]
signals are the
denominator. These two sets of signals are passed to the
lpm_divide
module where the quotient and
remainder are calculated. The divider calculates the quotient and remainder with a one-stage pipeline.
The quotient and remainder are then fed via signals
quotient[7..0]
and
remain[7..0]
back to the
ALTDDIO_BIDIR megafunction. The ALTDDIO_BIDIR megafunction then drives the data out
through pins
DDR_BIDIR8[7..0]
at double the data rate.
Implement the Divider Design
This section describes how to assign the Stratix EP1S10F780C6 device to the project and compile the
project.
1. With the ex2.qar project open, on the Assignments menu, click Settings. The Settings dialog box
displays.
2. In the Category list, select Device.
3. To answer Which device family will you be using?, select Stratix.
4. Under Target device, select Specific device selected in ‘Available devices’ list.
5. In the Available devices list, select EP1S10F780C6.
6. Under Show in ‘Available devices’ list, select FBGA as the Package, Pin count of 780, Speed grade of
6, and turn on Show Advanced Devices.
7. Click OK.
8. On the Processing menu, click Start Compilation.
9. When the Full Compilation was successful box displays, click OK.
Functional Results—Simulate the Divider Design in the ModelSim-Altera Software
Simulate the design in the ModelSim-Altera software to generate a waveform display of the device
behavior.
To set up the ModelSim-Altera software, follow these steps:
1. Unzip the ALTDDIO_ex2_msim.zip file to any working directory on your PC.
2. Browse to the folder in which you unzipped the files and open the ALTDDIO_ex2.do file in a text
editor.
3. In line 1 of the ALTDDIO_ex2.do file, replace <insert_directory_path_here> with the directory path
of the appropriate library files. For example,
C:/altera/71/modelsim_ae/altera/verilog/stratix
4. On the File menu, click Save.
5. Start ModelSim-Altera.
6. On the File menu, click Change Directory.
7. Select the folder in which you unzipped the files. Click OK.
8. On the Tools menu, click Execute Macro.
9. Select the ALTDDIO_ex2.do file and click Open. This is a script file for ModelSim that automates all
the necessary settings for the simulation.
10.Verify the results by looking at the Waveform Viewer window.
You can rearrange signals, remove redundant signals, and change the radix by modifying the script in
the ALTDDIO_ex2.do file.
16 Implement the Divider Design
UG-DDRMGAFCTN
2015.01.23
Altera Corporation Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide
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