Altera Double Data Rate I/O - Manual (Page 19)

Name Required Description
oe
No Output enable for the
dataout
port. Active-high
signal. You can add an inverter if you need an active-
low
oe
.
sclr
No Synchronous clear input. The
sclr
and
sset
ports
cannot be connected at the same time. The
sclr
port
is available for Arria GX, Stratix III, Stratix II,
Stratix II GX, Stratix, Stratix GX, HardCopy II, and
HardCopy Stratix devices only.
sset
No Synchronous set input. The
sclr
and
sset
ports
cannot be connected at the same time. The
sset
port
is available for Arria GX, Stratix III, Stratix II,
Stratix II GX, Stratix, Stratix GX, HardCopy II, and
HardCopy Stratix devices only.
Table 7: ALTDDIO_OUT Output Ports
Name Required Description
dataout[]
Yes DDR output data port. Output port
WIDTH
wide.
dataout
port should directly feed an output pin in
top-level design.
oe_out
No Output enable for the bidirectional
padio
port.
Output port [
WIDTH
–1..0] wide. This port is available
for Stratix III and Cyclone III devices only.
ALTDDIO_BIDIR IP Core Signals
This figure shows the ports for the ALTDDIO_BIDIR IP core.
Figure 11: ALTDDIO_BIDIR Ports
datain_h[ ]
inclock
inclocken
outclocken
oe
dataout_h[ ]
altddio_bidir
datain_l[ ]
outclock
dataout_l[ ]
padio[ ]
combout[ ]
dqsundelayedout[ ]
These tables list the output ports and the bidirectional ports for the ALTDDIO_BIDIR IP core.
Table 8: ALTDDIO_BIDIR Input Ports
Name Required Description
datain_h[]
Yes Input data to be output to the
padio
port at the rising
edge of the
outclock
port. Input port
[(WIDTH) - (1)
..0]
wide.
UG-DDRMGAFCTN
2015.01.23
ALTDDIO_BIDIR IP Core Signals 19
Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide Altera Corporation
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