Altera Temperature Sensor - Manual (Page 5)

Figure 3: Complete Design File
This figure shows the complete design file.
INPUT
VCC
clr
INPUT
VCC
clk
INPUT
VCC
ce
clr
clk
ce
tsd_s4
inst1
OUTPUT
tsdcalo[7..0]
OUTPUT
tsdcaldone
tsdcalo[7..0]
tsdcaldone
6. On the Processing menu, click Start Compilation.
7. When the Full Compilation was successful message box appears, click OK.
Using Clear Box Generator
You can use clear box generator, a command-line executable, to configure parameters that are in the
Altera Temperature Sensor IP core parameter editor. The clear box generator creates or modifies custom
IP core variations, which you can instantiate in a design file. The clear box generator generates IP core
variation file in Verilog HDL or VHDL format.
Note: Arria 10 Altera Temperature Sensor IP core does not support clear box generation format.
To generate the Altera Temperature Sensor IP core using the clear box generator, perform the following
steps:
1. Create a text file (.txt) that contains your clear box ports and parameter settings in your working
directory.
For example,
c:\altera\10.0\quartus\work\sample_param_test.txt.
This figure shows a sample text file to generate the Altera Temperature Sensor IP core.
Figure 4: Sample Text File for Clear Box Generator
UG-01074
2015.05.04
Using Clear Box Generator 5
Altera Temperature Sensor IP Core User Guide Altera Corporation
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