Altera Nios Development Board - Manual (Page 17)

Altera Corporation 1–9
September 2004 Nios Development Board Reference Manual, Stratix Edition
Board Components
The SDRAM device pins are connected to the Stratix device (see
Table 1–3 ). An SDRAM controller peripheral is included with the Nios II
development kit, allowing a Nios II processor to view the SDRAM device
as a large, linearly-addressable memory.
Table 1–3. SDRAM (U57) Pin Table (Part 1 of 2)
Pin Name Pin Number Connects to Stratix Pin
A0 25 AE4
A1 26 W12
A2 27 AC11
A3 60 W10
A4 61 AA11
A5 62 AC10
A6 63 AB11
A7 64 AC8
A8 65 AB10
A9 66 V11
A10 24 Y11
A11 21 AB7
BA0 22 AG19
BA1 23 AF19
DQ0 2 AH4
DQ1 4 AE5
DQ2 5 AG3
DQ3 7 AG5
DQ4 8 AG4
DQ5 10 AF4
DQ6 11 AH5
DQ7 13 AF5
DQ8 74 AE6
DQ9 76 AG6
DQ10 77 AH6
DQ11 79 AD6
DQ12 80 AF7
DQ13 82 AH7
DQ14 83 AG7
DQ15 85 AF6