Altera Nios Development Board - Manual (Page 36)

1–28 Altera Corporation
Nios Development Board Reference Manual, Stratix Edition September 2004
JTAG Connectors
The Stratix device can also supply a clock from the IO_PLL6_OUT0_p pin
to the Mictor connector (J25).
1 The 50 MHz oscillator (Y2) is socketed and can be changed by
the user. However, the EMP7128AE device configuration control
circuit and other Altera reference designs are not guaranteed to
work at different frequencies. It is the user’s responsibility to
accommodate a new clock oscillator when designing a system.
JTAG Connectors The Nios development board, has two 10-pin JTAG headers (J5 and J24)
compatible with Altera download cables, such as the USB Blaster
™ . Each
JTAG header connects to one Altera device and forms a single-device
JTAG chain. J24 connects to the Stratix device (U53), and J5 connects to the
EPM7128AE device (U3).
JTAG Connector to Stratix Device (J24)
J24 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the Stratix
device (U53) as shown in
Figure 1–22 . Altera Quartus II software can
directly configure the Stratix device with a new hardware image via an
Altera download cable as shown in
Figure 1–23 . In addition, the Nios II
IDE can access the Nios II processor JTAG debug module via a download
cable connected to the J24 JTAG connector.
Figure 1–22. JTAG Connector (J24) to Stratix Device