Zilog Z08470 - Manual (Page 126)

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7UGT /CPWCN
UM008101-0601 Direct Memory Access

the routine is being executed. Near the end of the routine, the CPU writes
an ENABLE INTERRUPTS command to the DIVA, which enables it to
generate a new interrupt.
This command is less extensive than the RESET AND DISABLE INTER-
RUPTS command because it does not reset the Interrupt Pending (IP) and
Interrupt Under Service (IUS) latches.
Figure 46. Write Register 6 Group
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
0 1
1 1 1
= C3 = Reset 0 0 0
Hex Command Name
0 1 = C7 = Reset Port A Timing 0 0 1
0 1 = C8 = Reset Port B Timing 0 1 0
0 1 = CF = Load 0 1 1
0 1 = D3 = Continue 1 0 0
1 0 = AF = Disable Interrupts 0 1 1
1 0 = AB = Enable Interrupts 0 1 0
1 0 = A3 = Reset and Disable Interrupts 0 0 0
1 0 = B7 = Enable after RETI 1 0 1
1 0 = BF = Read Status Byte 1 1 1
0 0 = 8B = Reinitialize Status Byte 0 1 0
1 0 = A7 = Initialize Read Sequence 0 0 1
1 0 = B3 = Force Ready 1 0 0
0 0 = 87 = Enable DMA 0 0 1
0 0 = 83 = Disable DMA 0 0 0
1 0 = BB = Read Mask Follows 1 1 0
Read Mask (1=Enable)
Status Byte
Byte Counter (Low Byte)
Byte Counter (High Byte)
Port A Address (Low Byte)
Port B Address (High Byte)
0
Port B Address (Low Byte)
Port A Address (High Byte)