Zilog Z08470 - Manual (Page 190)

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7UGT /CPWCN
UM008101-0601 Direct Memory Access

Figure 78. Write Register 2 Group
Figure 79. Write Register 3 Group
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
0 0
0
1
1 1
0
1
= Port B Address Decrements
0 = Port B is Memory
1 = Port B is I/O
Port B Variable
0 0
0
1
1 1
0
1 = Cycle Length = 3
= Cycle Length = 2
= Do Not Use
= Port B Address Increments
= Port B Address Fixed
Timing Byte
= Cycle Length = 4
WR Ends 1/2 Cycle Early = 0
RD Ends 1/2 Cycle Early = 0
MREQ Ends 1/2 Cycle Early = 0 0 = IORQ Ends 1/2 Cycle Early
0 0 0 0
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
Mask Byte (0 = Compare)
0 0 0
DMA Enable = 1
Interrupt Enable = 1
1 = Stop on Match
Match Byte