Zilog Z08470 - Manual (Page 166)

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UM008101-0601 Direct Memory Access

Figure 57. Z8000/Z80 Peripheral Interface
+5V
CLR
CLK
LS74
D Q
PRE
Q
LS32
LS10
LS10
LS32
LS04
Y0
Y1
Y2
Y3
Y4
Y5
RETI
G1
G2A
G2B
C
B
A
LS138
+5V
IORQ
LS06
To Z80
Peripherals
CE0
CE1
CE2
CE3
+5V
IORQ
CLOCK
R/W
VIACK
(Vectored Interrupt Acknowledge from ST3-ST0)
DS
AS
LA5
LA4
LA3
From Z8000
Data Bus LS08
RD
LS06
IORQ
PRE
CLR
CLK
LS74
D Q
Q