Zilog Z08470 - Manual (Page 85)

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7UGT /CPWCN
UM008101-0601 Direct Memory Access

system buses, it indicates a DMA-controlled write to a memory or
I/O port address.
RESET
Reset (input, active Low) is available in the CMOS PLCC version only. A
Low in this signal resets the DMA.
Figure 25. Pin Functions (CMOS PLCC Package Only)
System
Control
BUS
System
Data
Bus
Z80 DMA
CLK +5V GND
BAO
BAI
BUSREQ
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
System
Address
Bus
RDY
C5/WAIT
INT/PULSE
IEI
IEO
DMA
Control
Interrupt
Control
M1
IORQ
MREQ
RD
WR
RESET
C-MOS DMA
PLCC Package Only
BUS
Control