Sensoray 526 - Manual (Page 15)

15
Digital I/O
Digital I/O on model 526 consists of 8 signals, which can be configured as inputs or outputs in
groups of 4: DIO group 1 (DIO0-3) and DIO group 2 (DIO4-7). Interrupts can be generated on
rising or falling edges of DIO signals. Interrupt condition (rising or falling edge) can be selected
individually for every signal in group 1, and for group 2 as a whole. See Digital I/O Control
register description in the Registers section for the details.
Interrupts
Interrupts are controlled with 2 registers: Interrupt Enable register (IER) and Interrupt Status
register (ISR). ISR stores the status of various events, IER enables or disables the ability of those
events to generate an interrupt (Fig.4).
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ISR15
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IER0
IER1
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IER2
IER14
ISR1
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ISR2
IER15
IER13
ISR13
IRQ
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..........
ISR0
ISR14
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Fig.4. Simplified diagram of the interrupt controller.
When a specific interrupt condition is met, a corresponding bit is set in the ISR. If an interrupt was
enabled for this source by setting a corresponding bit of the IER to 1, the signal on the board’s
interrupt pin (selected with jumpers) goes high, generating an ISA interrupt. An interrupt handler
(software) must immediately disable the interrupts by writing a value of 0x0000 to the IER, which
results in the signal on the board’s interrupt pin going low. Next an interrupt handler detects the
source of the interrupt by analyzing the ISR, and resets the corresponding bits. (Note that the ISR
bits corresponding to the counters’ interrupt status are reset by resetting the corresponding bits in
the Counter Control/Status registers). When the interrupt processing is over, the interrupt handler
must restore the value of the IER. If a bit of the ISR has been set to 1 while the interrupt handler
was processing previous interrupt(s), the IRQ signal will go high again immediately after the IER is
restored, so no interrupts are lost.