Sundance SMT387 - Manual (Page 11)

Version 1.0.3 Page 11 of 42 SMT387 User Manual
TMS320C6415{xe "TMS320C6201"}
The processor will run with zero wait states from internal SRAM.
An on-board crystal oscillator provides the clock used for the C60 which then
multiplies this by 12 internally.
Boot Mode{xe "Boot Mode"}
The SMT387 is configured to boot from Flash only after a reset.
Flash boot:
1. The processor copies a bootstrap { XE "bootstrap program" }program from the
first part of the flash memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT387 then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured { XE "FPGA:configuration" }from data held in flash
memory and sets up the communication ports, the global bus and the
Sundance High-speed Buses. This step must have been completed before
data can be sent to the Comports from external sources such as the host or
other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the six
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports.
4. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is
around 4s for a SMT387 (600MHz clock).
A typical time to wait after releasing the board reset should be in excess of this delay,
but no damage will result if any of the I/Os are used before they are fully configured.
In fact, the comm. Ports will just produce a not ready signal when data transfer is
attempted during this time, and then continue normally after the FPGA is configured.
EMIF Control Registers{xe "EMIF Control Registers"}
The C6415 has two external memory interfaces (EMIFs). One of these is 64 bits
wide, the other 16 bits.