Sundance SMT387 - Manual (Page 12)

Version 1.0.3 Page 12 of 42 SMT387 User Manual
The C60 contains several registers that control the external memory interfaces
(EMIFs). {xe "memory space (CE0 to CE3)"}A full description of these registers can
be found in the C60 Peripherals Reference Guide.
The standard bootstrap will initialise these registers to use the following resources:
Memory
space
(EMIFA)
Resource Address range
Internal program memory
(1MB) 0x00000000 - 0x000FFFFF
CE0 SDRAM (2x 8MB chips) 0x80000000 - 0x807FFFFF
CE3 Virtex 0xB0000000 - 0xBFFFFFFF
Memory
space
(EMIFB)
Resource Address range
CE1 1 st / 3 rd section of flash (2MB
each)
0x64000000 – 0x641FFFFF
CE2 2 nd / 4 th section of flash (2MB
each)
0x68000000 – 0x681FFFFF
SDRAM{xe "RAM"}
Memory space CE0 is used to access 16MB of SDRAM over EMIFA. The SDRAM
operates at one quarter (or one sixth) of the core clock speed (with a max frequency
of 133MHz). Depending upon the application, the best performance may be obtained
whilst running the DSP at a lower clock speed. Eg. At 600MHz, the external EMIF will
only run at 100MHz (core clock / 6, as we are constrained by the TI imposed limit of
133MHz). But if the core were running at 533MHz, then the EMIF would be at the
max possible speed of 133MHz (533/4). This speed adjustment is not a user option,
but must be adjusted during manufacture.
The EMIFA CE0 memory space control register should be programmed with the
value 0x00000030.
Note that the DSP only has 20 address pins on the EMIFA, but since address bits are
multiplexed for SDRAM a maximum addressable space of 128MB is possible.
FLASH{xe "Flash"}
An 8MB Flash ROM{ XE "Flash:protection algorithm" } device is connected to the
C60 EMIFB.
The ROM holds boot code for the C60, configuration data for the FPGA, and optional
user-defined code.