Sundance SMT365 - Manual (Page 11)

Version 2.3 Page 11 of 28 SMT365 User Manual
ZBTRAM
Memory space CE0 is used to access 8MB of ZBTRAM over the EMIFA. It is mapped
as a 64-bit memory.
The speed of the ZBTRAM is dependent on the processor variant. Using the C6416,
the ZBTRAM will operate at 133MHz maximum. It operates at one quarter or one
sixth of the core clock speed.
The EMIFA CE0 memory space control register should be programmed with the
value 0x000000E0.
Note that depending upon the application; the best performance may be obtained
whilst running the DSP at a lower clock speed. I.e. at 600MHz, the external EMIF will
only run at 100MHz (core clock/6, as we are constrained by the TI imposed limit of
133MHz). But if the core were running at 533MHz, then the EMIF would be at the
maximum limit possible of 133MHz (a quarter of 533). This speed adjustment is not a
user option, but must be adjusted during manufacture.
Note also that the DSP only has 20 address pins on the EMIFA and cannot therefore
directly address more than 8MB of SRAM (the ZBTRAM is a type of SRAM with non-
multiplexed address pins). It requires the use of a paging mechanism to access
more. On the SMT365 there is a single page bit which is connected directly to the
most significant bit of the ZBTRAM (bit 20). This bit is controlled by a register
accessed on EMIFB CE3 address space (0x6C04000X). A write to the addresses
shown below (data = don’t care) will have the following effect:
Address ZBTRAM Address
bit 20 state
0x6C040000 0
0x6C040001 1
Note that for smaller ZBTRAM chipsets there is no need to set this bit as all memory
will be directly accessible to the DSP.