Sundance SMT365 - Manual (Page 8)

Version 2.3 Page 8 of 28 SMT365 User Manual
Architecture Description
DSP
The Texas Instruments DSP can run at up to 600MHz. The DSP is doted of 8MBytes
of Zero Bus Turnaround RAM (ZBTRAM).
The DSP is a TMS320C6416 type.
This is a fixed-point digital signal processor provided by Texas Instruments. The
processor will run with zero wait states from internal SRAM. The internal memory is
1MB in size and can be partitioned between normal SRAM and L2 cache.
An on-board crystal oscillator provides the clock used for the DSP which them
multiplies this by twelve internally.
Boot Mode
The DSP is connected to the on-board flash ROM that contains the Sundance
bootloader and the FPGA bitstream.
Following reset, the DSP will automatically load the data from the flash ROM into its
internal program memory at address 0 and then start executing from there. All this
code is the Sundance bootloader, and it is made up of two parts: FPGA configuration
and processor configuration. FPGA configuration uses data in the ROM to configure
the FPGA. A processor configuration sets the processor into a standard state by
writing into the DSP internal registers of the EMIF. Then it configures the FPGA from
the data held in the flash ROM.
Note that two control register bits are needed for this purpose, one to put the FPGA
into a ‘waiting for configuration’ state, and another to actually transfer the
configuration data. The PROG pin (causes the FPGA to enter the non-configured
state) is accessed at address 0x6C02000X. Writing to address 0x6C020000 will
assert this pin, and address 0x6C0200001 will de-assert this pin.
The configuration data clock is accessed at address 0x6C080001. Each bit of the
FPGA’s configuration bit-stream must be serially clocked through this address.
The bootloader is executed. It will continually check the six comports until data
appears on one of them. This will next load a program in boot format from this
comport. Note that the bootloader will not read data arriving on other comports.
Finally the control is passed to the loaded DSP application.
The DSP will take approximately about 1000ms to configure the FPGA following
reset, assuming a 600MHz clock. The external devices implemented in the FPGA
(such as comports) must not be used during this configuration.