Endura RADISYS KP915GV - Manual (Page 27)

KP915GV Product Manual
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• Support for non-ECC memory, unbuffered DIMMs only, in 256MB, 512MB, 1GB, and 2GB
sizes, which may be installed as single DIMMs if desired. If a total of 4GB of DIMMs is
installed, the maximum available memory will be approximately 3.24GB, with the balance of
the address space being consumed by other resources in the system.
• I/O Voltage of 1.8V for DDR2.
• Directly support only two channels of non-ECC DDR2 DIMMs.
• Supports maximum memory bandwidth of 4.2GB/s in single-channel or dual channel
asymmetric mode, or 8.5GB/s in dual-channel interleaved mode assuming DDR2 533MHz.
• For dual interleaved mode, DIMMs must be installed in matched pairs, installed in DIMM
sockets with identical color (e.g. locations DIMM1 and DIMM3, then DIMM2 and DIMM4).
• Supports 256Mb, 512Mb, and 1Gb technologies for x8 and x16 non-ECC DDR2 devices.
• Supports four banks for all DDR2 devices up to 512Mb densities. Supports eight banks for 1Gb
DDR2 devices.
• Maximum DRAM address decode space of 4GB. (Assuming 32-bit addressing)
• Supports opportunistic refresh scheme.
• Supports page sizes of 4KB, 8KB, 16KB and 32 KB. Note 32KB is for dual-channel operation
only.
• Supports up to 16 simultaneous open pages per channel
• Serial Presence Detect (SPD) scheme for DIMM detection support.
• Dual channel DDR2 for 4 X 240 pin DIMM connectors
• Support for Serial Presence Detect (SPD)
• Support for Suspend to RAM (STR) using CKE, S3 ACPI state
PCI Express Graphics Interface
•
One, 16-lane PCI Express port intended for Graphics Attach, fully compliant to the PCI
Express Base Specification revision 1.0a
• A base PCI Express frequency of 2.5Gb/s only.
• Raw bit-rate on the data pins of 2.5Gb/s, resulting in the real bandwidth per pair of 250MB/s
given the 8b/10b encoding used to transmit data across this interface.
• Maximum theoretical realized bandwidth on the interface of 4GB/s in each direction
simultaneously, for an aggregate of 8GB/s when x16.
• PCI Express Enhanced Addressing Mechanism. Accessing the device configuration space in
the flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering).
DMI
•
A chip-to-chip connection interface to Intel ICH6.
• 2GB/s point-to-point DMI to ICH6 (1GB/s each direction).
• 100MHz reference clock (shared with PCI Express Graphics Attach).
• 32-bit downstream addressing .
2.7 Video
• Integrated Intel® GMA900 video controller
1. Intel Infrastructure Processor Division (IPD) group Embedded Graphics or Graphics Media
Accelerator (GMA) (Extreme) drivers and video BIOS
• Analog RGB output with DDC2B
1. Graphics resolution up to 2048 x 1536 pixels with 32-bit color support at 75Hz
2. 15-pin D-sub connector