Eurotech Appliances VIPER / VIPER-LITE PXA255 User Manual
Page 36
VIPER Technical Manual
Detailed hardware description
© 2007 Eurotech Ltd Issue E
36
STN panel data bit mapping to the VIPER
Panel data bus bit
Dual scan colour STN Single scan colour STN Dual scan mono STN
FPD 15
DL7(G)
-
-
FPD 14
DL6(R)
-
-
FPD 13
DL5(B)
-
-
FPD 12
DL4(G)
-
-
FPD 11
DL3(R)
-
-
FPD 10
DL2(B)
-
-
FPD 9
DL1(G)
-
-
FPD 8
DL0(R)
-
-
FPD 7
DU7(G)
D7(G)
DL3
FPD 6
DU6(R)
D6(R)
DL2
FPD 5
DU5(B)
D5(B)
DL1
FPD 4
DU4(G)
D4(G)
DL0
FPD 3
DU3(R)
D3(R)
DU3
FPD 2
DU2(B)
D2(B)
DU2
FPD 1
DU1(G)
D1(G)
DU1
FPD 0
DU0(R)
D0(R)
DU0
Below is a table covering the clock signals required for passive and active type
displays:
VIPER
Active display signal (TFT)
Passive display signal (STN)
PCLK Clock
Pixel
Clock
LCLK
Horizontal Sync
Line Clock
FCLK
Vertical Sync
Frame Clock
BIAS DE
(Data
Enable)
Bias
The display signals are +3.3V compatible; the VIPER contains power control circuitry
for the flat panel logic supply and backlight supply. The flat panel logic is supplied with
a switched 3.3V (default) or 5V supply, see section
LCD Supply Voltage – LK8 on JP2
page
for details. The backlight is supplied with a switched 5V supply for the
inverter.
There is no on-board protection for these switched supplies! Care must be
taken during power up/down to ensure the panel is not damaged due to the
input signals being incorrectly configured.