Document Outline

• Table of Contents
  • List of Figures
  • List of Tables
• 1.0 System Overview
  • 1.1 Functional Summary
  • 1.1.1 Transmit Section
  • 1.1.2 Receive Section
  • 1.1.3 Timing Recovery and Clock Interface
  • 1.1.4 Microcomputer Interface
  • 1.1.5 Test and Diagnostic Interface (JTAG)
  • 1.2 Applications
    • 1.2.1 Voice/Data Pairgain
    • 1.2.2 Internet Connectivity Transport
    • 1.2.3 ISDN Basic Rate Interface Concentrator
  • 1.3 Pin Descriptions
• 2.0 Functional Description
  • 2.1 Transmit Section
    • 2.1.1 Symbol Source Selector/Scrambler
    • 2.1.2 Variable Gain Digital-to-Analog Converter
    • 2.1.3 Pulse-Shaping Filter
    • 2.1.4 Line Driver
  • 2.2 Receive Section
    • 2.2.1 Variable Gain Amplifier
    • 2.2.2 Analog-to-Digital Converter
    • 2.2.3 Digital Signal Processor
      • 2.2.3.1 Digital Front-End
      • 2.2.3.2 Offset Adjustment
      • 2.2.3.3 DC Level Meter
      • 2.2.3.4 Signal Level Meter
      • 2.2.3.5 Overflow Detection a...
      • 2.2.3.6 Far-End Level Meter
      • 2.2.3.7 Far-End Level Alarm
    • 2.2.4 Echo Canceler
      • 2.2.4.1 Linear Echo Canceler (LEC)
      • 2.2.4.2 Nonlinear Echo Canceler (NEC)
    • 2.2.5 Equalizer
      • 2.2.5.1 Digital Automatic Gain Control...
      • 2.2.5.2 Feed Forward Equalizer (FFE)
      • 2.2.5.3 Error Predictor (EP)
      • 2.2.5.4 Decision Feedback Equalizer 2....
      • 2.2.5.5 Microcoding
    • 2.2.6 Detector
      • 2.2.6.1 Slicer
      • 2.2.6.2 Peak Detector (PKD)
      • 2.2.6.3 Error Signals
      • 2.2.6.4 Scrambler Module
      • 2.2.6.5 Sync Detector
      • 2.2.6.6 Detector Meters
  • 2.3 Timing Recovery and Clock Interface
    • 2.3.0.7 Timing Recovery Circuit
    • 2.3.0.8 Crystal Amplifier
  • 2.4 Channel Unit Interface
  • 2.5 Microcomputer Interface
    • 2.5.1 Source Code
    • 2.5.2 Microcomputer Read/Write
      • 2.5.2.1 RAM Access Registers
      • 2.5.2.2 Multiplexed Address/Data Bus
      • 2.5.2.3 Separated Address/ D...
    • 2.5.3 Interrupt Request
    • 2.5.4 Reset
    • 2.5.5 Registers
    • 2.5.6 Timers
  • 2.6 Test and Diagnostic Interface (JTAG)
• 3.0 Registers
  • 3.1 Conventions
  • 3.2 Register Summary
    • 3.2.1 0x00—Global Modes and Status Register (glo...
    • 3.2.2 0x01—Serial Monitor Source Select Register...
    • 3.2.3 0x02—Interrupt Mask Register Low (mask_low...
    • 3.2.4 0x03—Interrupt Mask Register High (mask_hi...
    • 3.2.5 0x04—Timer Source Register (timer_source)
    • 3.2.6 0x05—IRQ Source Register (irq_source)
    • 3.2.7 0x06—Channel Unit Interface Modes Register...
    • 3.2.8 0x07—Receive Phase Select Register (receiv...
    • 3.2.9 0x08—Linear Echo Canceller Modes Register ...
    • 3.2.10 0x09—Nonlinear Echo Canceller Modes Regis...
    • 3.2.11 0x0A—Decision Feedback Equalizer Modes Re...
    • 3.2.12 0x0B—Transmitter Modes Register (transmit...
    • 3.2.13 0x0C—Timer Restart Register (timer_restar...
    • 3.2.14 0x0D—Timer Enable Register (timer_enable)...
    • 3.2.15 0x0E—Timer Continuous Mode Register (time...
    • 3.2.16 0x0F—Test Register (reserved2)
    • 3.2.17 0x10, 0x11—Startup Timer 1 Interval Regis...
    • 3.2.18 0x12, 0x13—Startup Timer 2 Interval Regis...
    • 3.2.19 0x14, 0x15—Startup Timer 3 Interval Regis...
    • 3.2.20 0x16, 0x17—Startup Timer 4 Interval Regis...
    • 3.2.21 0x18, 0x19—Meter Timer Interval Register ...
    • 3.2.22 0x20—Test Register (reserved9)
    • 3.2.23 0x1A, 0x1B—SNR Alarm Timer Interval Regis...
    • 3.2.24 0x1C, 0x1D—General Purpose Timer 3 Interv...
    • 3.2.25 0x1E, 0x1F—General Purpose Timer 4 Interv...
    • 3.2.26 0x21—ADC Control Register (adc_control)
    • 3.2.27 0x22—PLL Modes Register (pll_modes)
    • 3.2.28 0x23—Test Register (reserved10)
    • 3.2.29 0x24, 0x25—Timing Recovery PLL Phase Offs...
    • 3.2.30 0x26, 0x27—Receiver DC Offset Register (d...
    • 3.2.31 0x28—Transmitter Calibration Register (tx...
    • 3.2.32 0x29—Transmitter Gain Register (tx_gain)
    • 3.2.33 0x2A, 0x2B—Noise-Level Histogram Threshol...
    • 3.2.34 0x2C, 0x2D—Error Predictor Pause Threshol...
    • 3.2.35 0x2E—Scrambler Synchronization Threshold ...
    • 3.2.36 0x30, 0x31—Far-End High Alarm Threshold R...
    • 3.2.37 0x32, 0x33—Far-End Low Alarm Threshold Re...
    • 3.2.38 0x34, 0x35—SNR Alarm Threshold Register (...
    • 3.2.39 0x36, 0x37—Cursor Level Register (cursor_...
    • 3.2.40 0x38, 0x39—DAGC Target Register (dagc_tar...
    • 3.2.41 0x3A—Symbol Detector Modes Register (dete...
    • 3.2.42 0x3B—Peak Detector Delay Register (peak_d...
    • 3.2.43 0x3C—Digital AGC Modes Register (dagc_mod...
    • 3.2.44 0x3D—Feed Forward Equalizer Modes Registe...
    • 3.2.45 0x3E—Error Predictor Modes Register (ep_m...
    • 3.2.46 0x40, 0x41—Phase Detector Meter Register ...
    • 3.2.47 0x42—Overflow Meter Register (overflow_me...
    • 3.2.48 0x44, 0x45—DC Level Meter Register (dc_me...
    • 3.2.49 0x46, 0x47—Signal Level Meter Register (s...
    • 3.2.50 0x48, 0x49—Far-End Level Meter Register (...
    • 3.2.51 0x4A, 0x4B—Noise Level Histogram Meter Re...
    • 3.2.52 0x4C, 0x4D—Bit Error Rate Meter Register ...
    • 3.2.53 0x4E—Symbol Histogram Meter Register (sym...
    • 3.2.54 0x50, 0x51—Noise Level Meter Register (nl...
    • 3.2.55 0x5E, 0x5F— PLL Frequency Register (pll_f...
    • 3.2.56 0x70—LEC Read Tap Select Register (linear...
    • 3.2.57 0x71—LEC Write Tap Select Register (linea...
    • 3.2.58 0x72—NEC Read Tap Select Register (nonlin...
    • 3.2.59 0x73—NEC Write Tap Select Register (nonli...
    • 3.2.60 0x74—DFE Read Tap Select Register (dfe_ta...
    • 3.2.61 0x75—DFE Write Tap Select Register (dfe_t...
    • 3.2.62 0x76—Scratch Pad Read Tap Select (sp_tap_...
    • 3.2.63 0x77—Scratch Pad Write Tap Select (sp_tap...
    • 3.2.64 0x78—Equalizer Read Select Register (eq_a...
    • 3.2.65 0x79—Equalizer Write Select Register (eq_...
    • 3.2.66 0x7A—Equalizer Microcode Read Select Regi...
    • 3.2.67 0x7B—Equalizer Microcode Write Select Reg...
    • 3.2.68 0x7C–0x7F—Access Data Register (access_da...
• 4.0 Electrical & Mechanical Specifications
  • 4.1 Absolute Maximum Ratings
  • 4.2 Recommended Operating Conditions
  • 4.3 Electrical Characteristics
  • 4.4 Clock Timing
  • 4.5 Channel Unit Interface Timing
  • 4.6 Microcomputer Interface Timing
    • 4.6.1 Test and Diagnostic Interface Timing
    • 4.6.2 Analog Specifications
    • 4.6.3 Test Conditions
  • 4.7 Timing Measurements
  • 4.8 Mechanical Specifications