59 0x73—nec write tap select register (nonli, 60 0x74—dfe read tap select register (dfe_ta, 61 0x75—dfe write tap select register (dfe_t – Rockwell SoniCrafter BT8960 User Manual
Page 78: 62 0x76—scratch pad read tap select (sp_tap
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3.0 Registers
3.1 Conventions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
3.2.59 0x73—NEC Write Tap Select Register (nonlinear_ec_tap_select_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals.
When written, it causes the lowest-order 14 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–
0x7F] to be subsequently written to the selected NEC coefficient within two symbol periods. Does not affect the
value of the access data register.
3.2.60 0x74—DFE Read Tap Select Register (dfe_tap_select_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 57 decimals.
When written, it causes the selected 16-bit coefficient of the DFE to be subsequently loaded into the lowest-
order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within two symbol periods. Does
not affect the value of the coefficient.
3.2.61 0x75—DFE Write Tap Select Register (dfe_tap_select_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 57 decimals.
When written, it causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–
0x7F] to be subsequently written to the selected DFE coefficient within two symbol periods. Does not affect the
value of the access data register.
3.2.62 0x76—Scratch Pad Read Tap Select (sp_tap_select_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals.
When written, it causes the selected 8-bit scratch pad memory location to be subsequently loaded into the low-
est-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within two symbol periods.
Does not affect the value of the memory.
7
6
5
4
3
2
1
0
–
–
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
7
6
5
4
3
2
1
0
–
–
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
7
6
5
4
3
2
1
0
–
–
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
7
6
5
4
3
2
1
0
–
–
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]