Rockwell SoniCrafter BT8960 - Manual (Page 20)

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1.0 System Overview
1.3 Pin Descriptions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
Table 1-2. Hardware Signal Definitions (1 of 4)
Pin Label Signal Name I/O Definition
Microcomputer Interface (MCI)
MOTEL Motorola/Intel I Selects between Motorola and Intel handshake conventions for the RD/DS and
WR/R/W signals.
MOTEL = 1 for Motorola protocol: DS, R/W
MOTEL = 0 for Intel protocol: RD, WR
ALE Address Latch
Enable I Falling-edge-sensitive input. The value of AD[7:0] when MUXED = 1, or
ADDR[7:0] when MUXED = 0, is internally latched on the falling edge of ALE.
CS Chip Select I Active-low input used to enable read/write operations on the Microcomputer
Interface (MCI).
RD/DS Read/Data Strobe I Bimodal input for controlling read/write access on the MCI.
When MOTEL = 1 and CS = 0, RD/DS behaves as an active-low data strobe
DS. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data is
internally latched from AD[7:0] on the rising edge of DS when R/W = 0.
When MOTEL = 0 and CS = 0, RD/DS behaves as an active-low read strobe
RD. Internal data is output on AD[7:0] when RD = 0. Write operations are not
controlled by RD in this mode.
WR / R/W Write/
Read/Write I Bimodal input for controlling read/write access on the MCI.
When MOTEL = 1 and CS = 0, WR/R/W behaves as a read/write select line
R/W. Internal data is output on AD[7:0] when DS = 0 and R/W = 1. External data
is internally latched from AD[7:0] on the rising edge of DS when R/W = 0.
When MOTEL = 0 and CS = 0, WR/R/W behaves as an active-low write strobe
WR. External data is internally latched from AD[7:0] on the rising edge of WR.
Read operations are not controlled by WR in this mode.
AD[7:0] Address-
Data[7:0] I/O 8-bit bidirectional multiplexed address-data bus. AD[7] = MSB, AD[0] = LSB.
Usage is controlled using the MUXED signal as defined below.
ADDR[7:0] Address Bus[7:0]
(Not Multiplexed) I Provides a glueless interface to microcomputers with separate address and data
buses. ADDR[7] = MSB, ADDR[0] = LSB. Usage is controlled using the MUXED
signal.
MUXED Addressing
Mode Select I Controls the MCI addressing mode.
When MUXED = 1, the MCI uses AD[7:0] as a multiplexed signal for address
and data (typical of Intel processors).
When MUXED = 0, the MCI uses ADDR[7:0] as the address input and
AD[7:0] for data only (typical of Motorola processors).
READY Ready OD Active-low, open-drain output that indicates that the MCI is ready to transfer
data. Can be used to signal the microcomputer to insert wait states.
IRQ Interrupt Request OD Active-low, open-drain output that indicates requests for interrupt. Asserted
whenever at least one unmasked interrupt flag is set. Remains inactive whenever
no unmasked interrupt flags are present.
RST Reset I Asynchronous, active-low, level-sensitive input that places the transceiver in an
inactive state by setting the power-down mode bit of the Global Modes and Sta-
tus Register [global_modes; 0x00], and zeroing the clk_freq[1,0] bits of the PLL
Modes Register [pll_modes; 0x22], and the hclk_freq[1,0] bits of the Serial
Monitor Source Select Register [serial_monitor_source; 0x01]. All RAM con-
tents are lost. Does not affect the state of the test access port which is reset
automatically at power-up only.