3 timing recovery and clock interface, 3 timing recovery and clock interface, Bt8960 – Rockwell SoniCrafter BT8960 User Manual
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2.0 Functional Description
2.3 Timing Recovery and Clock Interface
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
2.3 Timing Recovery and Clock Interface
The timing recovery and clock interface block diagram consists of the timing
recovery circuit and the crystal amplifier, as detailed in Figure 2-5. The main pur-
pose of this circuitry is to recover the clock from the received data. Control fields
include the hclk_freq[1,0] bits of the Serial Monitor Source Select Register
[serial_monitor_source; 0x01], the PLL Modes Register [pll_modes; 0x22], the
Timing Recovery PLL Phase Offset Register [pll_phase_offsset_low,
pll_phase_offset_high; 0x24, 0x25] and the PLL Frequency Register
[pll_frequency_low, pll_frequency_high; 0x5E, 0x5F]. See the Register section
of this datasheet for descriptions of these control fields.
Figure 2-5. Timing Recovery and Clock Interface Block Diagram
HCLK (35)
QCLK (87)
XOUT (36)
XTALI (40)
XTALO (39)
C10
C11
Digital Ground
Y1
Timing
Recovery
Circuit
Detected
Symbol
Equalizer
Error
Crystal
Amplifier
Control
Registers
Phase Detector
Meter Register
[0x40, 0x41]