Rockwell SoniCrafter BT8960 - Manual (Page 34)

24
2.0 Functional Description
2.2 Receive Section
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
2.2.5.2 Feed Forward
Equalizer (FFE)
The Feed Forward Equalizer (FFE) removes precursors from the received signal.
The FFE may be operated in a special adapt last mode. In this mode, which is
useful during startup, only the last coefficient is updated. The last coefficient is
the one which is multiplied with the oldest data sample, (sample #7).
A freeze coefficient mode may be specified via the microcomputer interface.
This mode disables the coefficient updates only. A special mode exists to zero all
of the coefficients. It is also enabled through the microcomputer interface. Indi-
vidual FFE coefficients can be read and written through the microcomputer inter-
face. Adaptation should be frozen prior to reading or writing coefficients.
2.2.5.3 Error
Predictor (EP)
The Error Predictor (EP) improves the performance of the equalizer by prognosti-
cating errors before they occur. A freeze coefficient mode may be specified via
the microcomputer interface. This mode disables the coefficient updates only. A
special mode exists to zero all of the coefficients; it is also enabled through the
microcomputer interface. Individual EP coefficients can be read and written
through the microcomputer interface. Adaptation should be frozen prior to read-
ing or writing coefficients.
2.2.5.4 Decision
Feedback Equalizer
(DFE)
The Decision Feedback Equalizer (DFE) removes postcursors from the received
signal. A freeze coefficient mode may be specified via the microcomputer inter-
face. This mode disables the coefficient updates only. A zero coefficients mode
exists to zero all of the coefficients; it is also enabled through the microcomputer
interface. A zero filter output mode exists to zero the output of the FIR with no
effect on the coefficients. It is also enabled through the microcomputer interface.
Individual DFE coefficients can be read and written through the microcomputer
interface. Adaptation should be frozen prior to reading or writing coefficients.
2.2.5.5 Microcoding The DAGC, FFE, and EP filters are implemented using an internal micropro-
grammable Digital Signal Processor (DSP) optimized for LMS filters. Internal
DSP micro-instructions are stored in an on-chip RAM. This microcode RAM is
loaded after powerup through the microcomputer interface when the transceiver is
initialized.
2.2.6 Detector
The detector converts the equalized received signal into a 2B1Q symbol and pro-
duces two error signals used in adapting the receiver equalizers. The signal detec-
tion uses two sub-blocks, a slicer, and a peak detector. Additionally, the detector
contains a scrambler and Bit Error Rate (BER) meter for use during the startup
sequence.
2.2.6.1 Slicer The slicer thresholds the equalized signal to produce a 2B1Q symbol. The input
to the slicer is the FFE output minus the DFE and EP outputs.
The slicer can operate in two modes: two-level and four-level. In the two-level
mode, used during the part of startup when the only transmitted symbols are +3 or
–3, the slicer threshold is set at zero.
When in four-level mode, the cursor level is specified via the microcomputer
interface. It is a 16-bit, 2’s complement number, but must be positive and less
than 0x2AAA for proper operation.