Rockwell SoniCrafter BT8960 - Manual (Page 90)

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4.0 Electrical & Mechanical Specifications
4.6 Microcomputer Interface Timing
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
Table 4-14. Microcomputer Interface Switching Characteristics
Symbol Parameter Minimum Maximum Units
49 Data Out Enable (Low Z) after Read Strobe Falling Edge (1) 2 ns
50 Data Out Valid after Read Strobe Low (1,7) 2* Tmclk +25 ns
51 Data Out Hold after Read Strobe Rising Edge (1) 2 ns
52 Data Out Disable (High Z) after Read Strobe High (1) 25 ns
53 IRQ Hold after Write Strobe Rising Edge (2,3) 5 ns
54 IRQ Delay after Write Strobe High (2,3) Tqclk ÷ 32 + 20 ns
55 Internal Register Delay after Write Strobe High (3,4) Tqclk ÷ 32 ns
56 Internal RAM Delay after Write Strobe High (3,5) 2*Tqclk ns
57 Access Data Register Delay after Write Strobe High (3,6) 2* Tqclk ns
58 READY Falling Edge after Write Strobe Low (3) 0 2*Tmclk +25 ns
59 READY Rising Edge after Write Strobe High (3) 0 50 ns
60 READY Falling Edge after Read Strobe Low (1) 0 2*Tmclk +25 ns
61 READY Rising Edge after Read Strobe High (1) 0 50 ns
62 Data Out Valid after READY low 10 ns
Notes: (1). Read Strobe is defined as RD and CS asserted in Intel mode, and DS and CS asserted when R/W is high in Motorola
mode.
(2). When writing an interrupt mask or status register.
(3). Write Strobe is defined as WR and CS asserted in Intel mode, and DS and CS asserted when R/W is low in Motorola
mode.
(4). Writes to internal registers are synchronized to an internal 64-times symbol-rate clock. Data is available for reading after
the specified time. This parameter may extend the overall read access time from internal register locations under high
bus speed/low symbol rate conditions.
(5). When performing an indirect write to RAM-based locations using a write select register [odd addresses: 0x71–0x7B]
and the Access Data Register. Subsequent writes to any read/write select register or the Access Data Register, as initiated
by a Write Strobe falling edge, is prohibited for the specified time. This parameter will extend the overall write access
time to RAM-based locations under normal bus speed/symbol rate conditions.
(6). When performing an indirect read from RAM-based locations using a read select register [even addresses: 0x70–0x7A]
and the Access Data Register. Subsequent writes to any read/write select register, as initiated by a Write Strobe falling
edge, is prohibited for the specified time. Data is available for reading from the Access Data Register after the specified
time. This parameter will extend the overall read access time from RAM-based locations under normal bus speed/sym-
bol rate conditions. Direct writes to the Access Data Register are as specified for internal registers.
(7). The timing listed is for the synchronous mode of the MCI. It can also be set to synchronous mode by setting bit 0 of the
reserved2 register (address 0x0F) to a 1. In this case the minimum timing changes to 40 us for symbol 39, and 50 us
for symbols 40 and 50. Synchronous mode is preferred because it reduces internal switching noise, however no signif-
icant performance degradation has been measured as a result of using the asynchronous mode.