MSI G52-S9617X1 User Manual
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BIOS Setup
PCI1/PCI2 M aster 0 WS Write
W hen [Enabled], writes to the PCI bus are executed with zero wait state.
PCI1/PCI2 Post Write
You can enable or disable the ability of the chipset to use a buffer for posted
writes initiated on the PCI bus. Setting options: [Disabled], [Enabled].
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select [Enabled] to support compliance with PCI specifica-
tion version 2.1.
Init Display First
This item specifies which VGA card is your primary graphics adapter. Settings: [PCI
Slot], [AGP].
AGP Aperture Size
This setting controls just how much system RAM can be allocated to AGP for video
purposes. The aperture is a portion of the PCI memory address range dedicated to
graphics memory address space. Host cycles that hit the aperture range are for-
warded to the AGP without any translation.