Motorola MVME2400 - Manual (Page 163)

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clock cycle. Instructions can be sent simultaneously to three types of
independent execution units (branch units, fixed-point units, and
floating-point units), where they can execute concurrently, but finish
out of order. PowerPC is used by Motorola, Inc. under license from
IBM.
PowerPC 601™ The first implementation of the PowerPC family of
microprocessors. This CPU incorporates a memory management
unit with a 256-entry buffer and a 32KB unified (instruction and
data) cache. It provides a 64-bit data bus and a separate 32-bit
address bus. PowerPC 601 is used by Motorola, Inc. under license
from IBM.
PowerPC 603™ The second implementation of the PowerPC family of
microprocessors. This CPU incorporates a memory management
unit with a 64-entry buffer and an 8KB (instruction and data) cache.
It provides a selectable 32-bit or 64-bit data bus and a separate 32-
bit address bus. PowerPC 603 is used by Motorola, Inc. under
license from IBM.
PowerPC 604™ The third implementation of the PowerPC family of
microprocessors currently under development. PowerPC 604 is used
by Motorola, Inc. under license from IBM.
PowerPC Reference Platform (PRP)
A specification published by the IBM Power Personal Systems
Division which defines the devices, interfaces, and data formats that
make up a PRP-compliant system using a PowerPC processor.
PowerStack™ RISC PC (System Board)
A PowerPC-based computer board platform developed by the
Motorola Computer Group. It supports Microsoft’s Windows NT
and IBM’s AIX operating systems.
PRP See PowerPC Reference Platform (PRP).
PRP-compliant See PowerPC Reference Platform (PRP).
PRP Spec See PowerPC Reference Platform (PRP).
PROM Programmable Read-Only Memory
PS/2 Personal System/2 (IBM)
QFP Quad Flat Package