Motorola MVME2400 - Manual (Page 62)

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Functional Description
3
❏ Clock counts represent best case alignment between PCI and
PPC60x clock domains. An exception to this is continuous
bandwidth which reflects the average affects of clock alignment.
PCI Originated
❏ Count represents number of PCI Bus clock cycles.
❏ Assumes write posting FIFO is initially empty
❏ L2 caching is not enabled, all transactions exclusively controlled by
the SMC.
❏ Does not include time taken to obtain grant for PCI Bus. The count
starts on the same clock period that FRAME_ is asserted.
❏ One clock request/one clock grant PPC60x bus arbitration.
❏ PPC60x bus traffic limited to PHB transactions only.
❏ Write posting and read adhead enabled.
❏ Default FIFO threshold settings.
❏ One cache line = 32 bytes.
SDRAM Memory
The MVME2400 SDRAM memory size can be 32MB, 64MB, or 128MB.
The SDRAM blocks are controlled by the Hawk ASIC which provides
single-bit error correction and double-bit error detection. ECC is
calculated over 72-bits.
The memory block size is dependant upon the SDRAM devices installed.
Installing five 64Mbit (16bit data) devices provides 32MB of memory.
With 64Mbit (8bit data) devices, there are two blocks consisting of 9
devices each that total 64MB per block. In this case, either block can be
populated for 64Mbytes or 128Mbytes of onboard memory. With 128Mbit
(8bit data) devices, the blocks can be populated for 128Mbytes and
256Mbytes. If 64Mbit (4bit data) devices are installed, there is one block