Motorola MVME2400 - Manual (Page 76)

3-28 Computer Group Literature Center Web Site
Functional Description
3
Interrupt Controller (MPIC)
The MPIC Interrupt Controller portion of the Hawk ASIC is designed to
handle various interrupt sources. The interrupt sources are:
❏ Four MPIC timer interrupts
❏ Processor 0 self interrupt
❏ Memory Error interrupt from the SMC
❏ Interrupts from all PCI devices
❏ Two software interrupts
❏ ISA interrupts (actually handles as a single 8259 interrupt at INT0)
Programmable Timers
Among the resources available to the local processor are a number of
programmable timers. Timers are incorporated into the PCI/ISA Bridge
(PIB) controller and the Hawk device (diagrammed in Figure 3-1). They
can be programmed to generate periodic interrupts to the processor.
Interval Timers
The PIB controller has three built-in counters that are equivalent to those
found in an 82C54 programmable interval timer. The counters are grouped
into one timer unit, Timer 1, in the PIB controller. Each counter output has
a specific function:
❏ Counter 0 is associated with interrupt request line IRQ0. It can be
used for system timing functions, such as a timer interrupt for a
time-of-day function.
❏ Counter 1 generates a refresh request signal for ISA memory. This
timer is not used in the MVME240x.
❏ Counter 2 provides the tone for the speaker output function on the
PIB controller (the
SPEAKER_OUT signal which can be cabled to an
external speaker via the remote reset connector). This function is not
used on the MVME240x.